As is known in the art, it is frequently desirable to couple high frequency energy such as radio frequency (RF) or microwave energy, between a pair of overlaying, bonded semiconductor wafers. This is sometimes referred to as Three Dimensional (3D) integration, see for example: a paper entitled “Reliability of key technologies in 3D integration’ by Chen-Ta Ko, Kuan-Neng Chen, Microelectronics Reliability 53 (2013) 7-17; a paper entitled “Low Cost of Ownership Scalable Copper Direct Bond Interconnected 3D IC Technology for Three Dimensional Integrated Circuit Applications “by Enquist et al, 978-1-4244-4512 2009 IEEE; and a paper entitled “MMIC Compatible Wafer-Level Packaging Technology” by P. Chang-Chien et al., 2007 International Conference on Indium Phosphide and Related Materials, 18, May 2007 Matsue, Japan.
As is also known in the art, in many applications it is desirable to provide a coaxial shield through silicon carrier wafers in 3D integration, as described in a paper entitled “Development of Coaxial Shield Via in Silicon Carrier for High Frequency Application” by Ho et al., 2006 Electronics Packaging Technology Conference pages 825-830.
As is also known in the art, a paper entitled “Recent developments using TowerJazz SiGe BiCMOS platform for mmWave and THz applications”, Arjun Kar-Roy et al., Passive and Active Millimeter-Wave Imaging XVI, edited by David A. Wikner, Arttu R. Luukanen, Proc. of SPIE Vol. 8715, 871505.® 2013 SPIE “CCC code: 0277-786X/13/$18 doi: 10.1117/12.1518475 reports radio frequency vias formed in silicon germanium (SiGe) BiCMOS technology. See also U. S. Patent Application Publication No. 2014/0054743, entitled “Isolated Through Silicon Vias in RF Technologies” Applicants Hurwitz; Paul D. et al., published Feb. 27, 2014.
As is also known in the art, large diameter copper filled vias are formed through relatively thick silicon layers. This results in high losses at these high frequency energies due to the conductivity of the silicon substrate. Another method used includes the use of small tungsten filled vias; however, while this method is good for high density 3D interconnect, it does not confine the field enough to produce a via with low high frequency energy losses.